lscpu - Ingenic JZRISC V4.15 FPU V0.0

Return To Ingenic JZRISC V4.15 FPU V0.0 System Information

Architecture:          mips
Byte Order:            Little Endian
CPU(s):                2
On-line CPU(s) list:   0,1
Thread(s) per core:    1
Core(s) per socket:    2
Socket(s):             1